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SX1211
WIRELESS & SENSING
7.3.1. Optimized Receive Cycle
The lowest-power Rx cycle is the following:
SX1211
IDD
IDDR
3.0mA typ.
IDDFS
1.3mA typ.
IDDST
65uA typ.
IDDSL
100nA typ.
Rx
time
SX1211 can be put in
Time
Any other mode
Wait
TS RE
Receiver is ready :
-RSSI sampling is valid after a 1/Fdev period
-Received data is valid
Wait
TS FS
Set SX1211 in Rx mode
Wait for Receiver settling
Wait
TS OSC
Set SX1211 in FS mode
Wait for PLL settling
Set SX1211 in Standby mode
Wait for XO settling
Figure 49: Optimized Rx Cycle
Note: If the lock detect indicator is available on an external interrupt pin of the companion uC, it can be used to
optimize TS_FS, without having to wait the maximum specified TS_FS.
Rev 8 – February 2013
Page 67 of 92
www.semtech.com
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